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Semester 3 : Notes : Logic System Design
Module 1:- Number systems, Operations & Codes
Syllabus
Decimal, Binary, Octal and Hexadecimal Number Systems- Number Base Conversions
Addition, Subtraction, Multiplication and Division of binary numbers
Representation of negative numbers- Complements, Subtraction with complements
Addition and subtraction of BCD, Octal and Hexadecimal numbers
Binary codes- Decimal codes, Error detection codes, Reflected code, Character coding
Character coding schemes - ASCII, EBCDIC
Module 2:- Boolean Algebra
Syllabus
Postulates of Boolean Algebra
Basic theorems and Properties of Boolean Algebra
Boolean Functions - Canonical and Standard forms
Simplification of Boolean Functions- Using Karnaugh- Map Method (up to five variables), Don’t care conditions, product of sums simplification, Tabulation Method
Digital Logic Gates- Implementation of Boolean functions using basic and universal gates
Module 3:- Combinational Logic Circuits
Syllabus
Design Procedure & Implementation of combinational logic circuits- Binary adders and subtractors, Binary Parallel adder, Carry look-ahead adder, BCD adder, Code converter, Magnitude Comparator, Decoder, Demultiplexer, Encoder, Multiplexer, Parity generator/ Checker
Module 4:- Sequential logic circuits
Syllabus
Flip-flops - SR, JK, T and D
Triggering Of Flip-Flops - Master-Slave Flip-Flops, Edge-Triggered Flip-Flops
Excitation table and characteristic equation
Registers - Register with the parallel load
Counter Design: Asynchronous Counters - Binary and BCD counters, timing sequences and state diagrams
Synchronous Counters - Binary Up-down counter, BCD counter
Module 5:- Shift Registers & Arithmetic Algorithms
Syllabus
Shift Registers - Serial In Serial Out, Serial In Parallel Out, Bidirectional Shift Register with Parallel load
Ring Counter, Johnson Counter - timing sequences and state diagrams
Algorithms for addition and subtraction of binary numbers in signed magnitude and 2's complement representations
Algorithm for addition and subtraction of BCD numbers
Representation of floating-point numbers, Algorithm for addition and subtraction of floating-point numbers
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Contributed By
1. Rahul A B
2. Jose Antony
3. Vivek K J
4. Joel Jaison
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